1. Field of the Invention
The present invention relates to a method of generating cell library data for large scale integrated circuits, and more particularly to a cell library data generating method that can very precisely extract the source-drain resistances of the miniaturized MOS transistors making up the cell and very precisely generate cell input-output characteristics.
2. Description of the Related Art
Application-specific integrated circuits (ASIC) are designed using multiple types of cells that are registered in a library. Each cell is composed of a single MOS transistor or a combination of multiple MOS transistors, and has a specific function (e.g., inverter, NAND, NOR, ENOR, RS-FF). A logic circuit designed using these cells is actually laid out only after it has been confirmed in a logic verification step that the logic of the logic circuit is correctly designed. Next, the delay time characteristics in this laid-out state are calculated, and timing verification is carried out to determine whether the intended operation can be performed based on the actual delay characteristic. The cell data stored in the library thus includes, in addition to layout data, further information such as the input-output characteristic and the delay time.
When a device is newly designed, the cells are designed using MOS transistors which conform to certain design rules. To achieve the logic function of a cell, a plurality of MOS transistors are connected together to make up the cell. Characteristic parameters for the MOS transistors within a cell, such as their gate widths, gate lengths, drain resistances and source resistances, can be determined from the specific construction of the transistors. Moreover, based on these characteristic parameters, information such as the cell input-output characteristic and delay time can be determined.
The drain resistances and source resistances of the MOS transistors making up a cell can generally be determined with RC extraction tools, and the cell input-output characteristic and delay time characteristic can be determined with a simulator tool. That is, device characteristics such as the parasitic resistance and parasitic capacitance of the MOS transistors making up a cell can be extracted using these RC extraction tools, and the cell characteristics such as the input-output characteristic can be determined using the simulator tool. Once it has been determined, the input-output characteristic is registered as cell library data.
Japanese Patent Application Laid-open No. 2000-133800 and Japanese Patent Application Laid-open No. 2003-256492 describe methods for determining the characteristic parameters of MOS transistors. These patent publications describe methods for evaluating MOS transistor characteristics and methods for evaluating contact resistances.